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Integrated Circuit Systems, Inc.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
FEATURES
* 5 differential 3.3V LVPECL outputs * Selectable differential clock inputs * CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * VCO range: 200MHz to 500MHz * External feedback for "zero delay" clock regeneration with configurable frequencies * Cycle-to-cycle jitter (RMS): 20ps (maximum) * Output skew: 70ps (maximum), within one bank * 3.3V supply voltage * -40C to 85C ambient operating temperature * Pin compatible with MPC993
GENERAL DESCRIPTION
The ICS87993I is a PLL clock driver designed specifically for redundant clock tree designs. The HiPerClockSTM device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signal frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance.
,&6
The ICS87993I Dynamic Clock Switch (DCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated.
PIN ASSIGNMENT
nQB0 nQB1 nQB2 QB0 QB1 QB2 VCC
24 23 22 21 20 19 18 17 nQA1 QA1 nQA0 QA0 VCC VCCA MAN_OVERRIDE PLL_SEL 25 26 27 28 29 30 31 32 1
nMR
VCC
16
VCC INP0BAD INP1BAD CLK_SELECTED VEE nEXT_FB EXT_FB VEE
ICS87993I
32-Lead QFP (LQFP) 7mm x 7mm x 1.4mm package body Y Package Top View
2
nALARM_RESET
15 14 13 12 11 10 9
3
CLK0
4
nCLK0
5
CLK_SEL
6
CLK1
7
nCLK1
8
VEE
BLOCK DIAGRAM
PLL_SEL CLK_SELECTED INP1BAD INP0BAD MAN_OVERRIDE ALARM_RESET SEL_CLK nCLK0 CLK0 nCLK1 CLK1 nEXT_FB EXT_FB nMR
87993AYI
Dynamic Switch Logic
nQB0 QB0 nQB1 QB1
/2 PLL /4
nQB2 QB2 nQA0 QA0 nQA1 QA1
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Integrated Circuit Systems, Inc.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
Type Input Description Active LOW Master Reset. When logic LOW, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs Pullup nQx to go high. When logic HIGH, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. When LOW, resets the input bad flags and aligns CLK_SELECTED Pullup with SEL_CLK. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup
TABLE 1. PIN DESCRIPTIONS
Number 1 Name nMR
2 3 4 5 6 7 8, 9, 12 10 11 13 14
nALARM_RESET CLK0 nCLK0 SEL_CLK CLK1 nCLK1 VEE EXT_FB nEXT_FB CLK_SELECTED INP1BAD
Input Input Input Input Input Input Power Input Input Output Output
Inver ting differential clock input. Clock select input. When LOW, selects CLK0, nCLK0 inputs. When Pulldown HIGH, selects CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Negative supply pins. Pulldown Differential external feedback. Pullup Differential external feedback. LOW, when CLK0, nCLK0 is selected, HIGH, when CLK1, nCLK1 is selected. LVCMOS / LVTTL interface levels. Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asser ted. Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asser ted. Core supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Analog supply pin. Manual override. When HIGH, disables internal clock switch circuitr y. Pulldown LVCMOS / LVTTL interface levels. Selects between the PLL and reference clock as the input to the Pullup dividers. When LOW, selects reference clock.When HIGH, selects PLL. LVCMOS / LVTTL interface levels.
15 16, 17, 24, 29 18, 19 20, 21 22, 23 25, 26 27, 28 30 31 32
INP0BAD VCC nQB2, QB2 nQB1, QB1 nQB0, QB0 nQA1, QA1 nQA0, QA0 VCCA MAN_OVERRIDE PLL_SEL
Output Power Output Output Output Output Output Power Input Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
87993AYI
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCA IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 80 15 Maximum 3.465 3.465 180 20 Units V V mA mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage LVCMOS Inputs LVCMOS Inputs SEL_CLK, MAN_OVERRIDE Input High Current nALARM_RESET, PLL_SEL, nMR SEL_CLK, MAN_OVERRIDE Input Low Current nALARM_RESET, PLL_SEL, nMR Output High Voltage; NOTE 1 Test Conditions Minimum 2 -0.3 VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -120 2.4 0.5 Typical Maximum 3.3 0.8 5 120 Units V V A A A A V V
IIL VOH
VOL Output Low Voltage; NOTE 1 NOTE 1: Outputs terminated with 50 to VCC/2. See Parameter Measurement Information Section, "3.3V Output Load AC Test Circuit diagram".
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C
Symbol IIH Parameter CLK0, CLK1, EXT_FB Input High Current nCLK0, nCLK1, nEXT_FB CLK0, CLK1, EXT_FB Input Low Current nCLK0, nCLK1, nEXT_FB Peak-to-Peak Input Voltage Test Conditions VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -120 0.15 1.3 VCC - 0.85 Minimum Typical Maximum 5 120 Units A A A A V V
IIL VPP
Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended appliations, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 1.0 VCC - 1.7 1.0 Units V V V
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C
Symbol fVCO tPWI CLKx to Q tPD Propagation Delay CLKx to EXT_FB; NOTE 2 PLL_SEL = LOW PLL_SEL = HIGH fVCO 360MHz PLL_SEL = HIGH fVCO 500MHz 20% to 80% @ 50MHz Parameter PLL VCO Lock Range Test Conditions Minimum 200 25 2.8 -150 -150 200 3.45 0 0 Typical Maximum 500 75 4.1 170 200 800 70 100 20 Tested at typical conditions 10 200 100 f 360MHz 45 50 25 400 200 55 20 10 Units MHz % ns ps ps ps ps ps ps/cycle ps/cycle ps/cycle ps/cycle % ps ms
tR / tF
Output Rise Time Output Skew; NOTE 3 Within Bank All Outputs 75MHz Output; NOTE 1, 4 150MHz Output; NOTE 1, 4 75MHz Output; NOTE 1, 5 150MHz Output; NOTE 1, 5
t sk(o)
PER/CYCLE
Rate of change of Periods
odc t jit(cc) tL
Output Duty Cycle Cycle-to-Cycle Jitter (RMS); NOTE 1 PLL Lock Time; NOTE 1
All parameters measured at fMAX unless noted otherwise. NOTE 1: These parameters are guaranteed by characterization. Not tested in production. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. NOTE 5: Specification holds for a clock switch between two signals no greater than out of phase. Delta period change per cycle is averaged over the clock switch excursion.
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
PARAMETER MEASUREMENT INFORMATION
VCC , VCCA = 2V VCC
Qx
SCOPE
nCLK0, nCLK1 V
PP
LVPECL
nQx
Cross Points
V
CMR
CLK0, CLK1 VEE
VEE = -1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
tsk(o)
nQAx, nQBx nQAx, nQBx
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
80% Clock Outputs
80% VSW I N G
nQAx, nQBx nQAx, nQBx
Pulse Width t
PERIOD
20% tR tF
20%
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
87993AYI
odc & tPERIOD
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tcycle n+1
Integrated Circuit Systems, Inc.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87993I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10 F 10
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
Zo = 50 FIN Zo = 50 Zo = 50 FOUT 50 50 VCC - 2V 5 2 Zo
3.3V 5 2 Zo
FOUT
FIN
RTT =
1 (VOH + VOL / VCC -2) -2
Zo
FIGURE 2A. LVPECL OUTPUT TERMINATION
87993AYI
RTT
Zo = 50 3 2 Zo 3 2 Zo
FIGURE 2B. LVPECL OUTPUT TERMINATION
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Integrated Circuit Systems, Inc.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87993AYI
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL HiPerClockS Input R1 50 R2 50 Zo = 50 Ohm nCLK HiPerClockS Input CLK
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
87993AYI
BY
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
Bank A or Bank B depending on the application. The decoupling capacitors should be physically located near the power pin. For ICS87993I, the unused outputs can be left floating.
SCHEMATIC EXAMPLE
Figure 5A shows a schematic example of the ICS87993I. In this example, the CLK0/nCLK0 input is selected as primary. The input is driven by an LVPECL driver. Feedback can be either from
VCC VCC VCC R16 1K R7 10 Zo = 50 VCCA C11 LVCMOS C16 10u VCC 0.01u R2 50 32 31 30 29 28 27 26 25 R1 50 R15 1K Zo = 50 +
U1 VCC Zo = 50 Ohm CLK_SEL Zo = 50 Ohm LVPECL Driv er R9 50 C7 (Option) 0.1u R10 50 ICS87993I R11 50 R2 1K 1 2 3 4 5 6 7 8
PLL_SEL MAN_OVR VCCA VCC QA0 nQA0 QA1 nQA1
C5 (Option) 0.1u VCC QB0 nQB0 QB1 nQB1 QB2 nQB2 VCC 24 23 22 21 20 19 18 17
R3 50
VCC Zo = 50 Ohm R5 50 Zo = 50 Ohm LVPECL Driv er R12 50 C6 (Option) 0.1u R13 50 R14 50 C8 (Option) 0.1u R6 50 R4 50
9 10 11 12 13 14 15 16
VEE EXT_FB nEXT_FB VEE CLK_SELECTED INP1BAD INP0BAD VCC
nMR nALM_RS CLK0 nCLK0 CLK_SEL CLK1 nCLK1 VEE
LVCMOS
LVCMOS
LVCMOS
(U1-16)
VCC
(U1-17)
(U1-24)
(U1-29)
C1 0.1uF
C2 0.1uF
C3 0.1uF
C4 0.1uF
FIGURE 5A. ICS87993I LVPECL SCHEMATIC EXAMPLE
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. * The differential 50 output traces should have same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The series termination resistors should be located as close to the driver pins as possible.
POWER
AND
GROUNDING
Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the
GND
R7 C16 C11 C4
VCC U1
Pin 1
C3
VCCA
VIA
50 Ohm Traces
C2
C1
FIGURE 5B. PCB BOARD LAYOUT FOR ICS87993I
87993AYI
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS87993I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS87993I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 180 = 624mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 624mW + 151mW = 775mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.775W * 42.1C/W = 117.6C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE qJA
FOR
32-PIN LQFP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
87993AYI
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3. Calculations and Equations.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87993I is: 2745
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
Marking ICS87993AYI ICS87993AYI Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87993AYI ICS87993AYIT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87993AYI
www.icst.com/products/hiperclocks.html
15
REV. B May 21, 2003
Integrated Circuit Systems, Inc.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
REVISION HISTORY SHEET Description of Change AC Table - deleted Note 6. Added "Wiring the Differential Input to Accept Single Ended Levels". Features Section - changed VCO max. from 360MHz to 500MHz. Pin Descriptions Table - revised nMR description. Pin Characteristics Table - changed CIN from max. 4pF to typical 4pF. Absolute Maximum Ratings - changed VO to IO and included Continuous Current and Surge Current AC Characteristics Table - changed fVCO from 360MHz to 500MHz. tPD - added test conditions to CLKx to EXT_FB. Added another line with 500MHz test conditions. odc - added test conditions. Added Differential Clock Input Interface in the Application Information section. Added Schematic Example. 5/21/03 Date 1/16/03
Rev A
Table T4
Page 4 7 1
T1 T2
2 2 3
B
T4
4
8 9 & 10
87993AYI
www.icst.com/products/hiperclocks.html
16
REV. B May 21, 2003

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